It has been pointed out in Ref. [1, 2], that one can use optimum variation lateral doping, shortly as VLD, to achieve highest breakdown voltage within a minimum distance on the surface. The breakdown voltage reached by using such method is close to the breakdown voltage of a one-sided abrupt parallel plane junction made by the same substrate. Furthermore, the methods of implementation of high-side devices as well as low-side devices by using optimum VLD were proposed in references [4, 5].
It has been proposed in Ref. [3] that the idea of optimum VLD, in its substantial physical mechanism, should be changed to optimum VLF, where F stands for flux density. A method to realize an optimum VLF has also been proposed in Ref. [3]. This method includes a film of high permittivity material covering on the semiconductor surface.
However, most popular technologies of integrated circuits are CMOS and BiCMOS technologies, and in such technologies, few can provide the necessary doses as well as depths of n-type and p-type impurities required according to Ref. [2] and [3]. Not to mention, almost no technology in integrated circuits contain a process to fabricate a material of a permittivity much higher than that of the semiconductor as required in Ref. [3]. Therefore, it is interesting to find a method to realize optimum VLF in a lateral voltage-sustaining region by conventional CMOS/BiCMOS technologies so that the high-voltage or power integrated circuits can be made cost-effectively.
The present invention provides a method to realize optimum variation lateral flux density by using the multiple insulator layers and the multiple conductive layers inherently contained in the conventional CMOS/BiCMOS technologies.